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MC14017B Decade Counter
The MC14017B is a five-stage Johnson decade counter with built-in code converter. High speed operation and spike-free outputs are obtained by use of a Johnson decade counter design. The ten decoded outputs are normally low, and go high only at their appropriate decimal time period. The output changes occur on the positive-going edge of the clock pulse. This part can be used in frequency division applications as well as decade counter or decimal decode display applications.
Features
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16 MC14017BCP AWLYYWWG 1
* * * * * * * * *
Fully Static Operation DC Clock Input Circuit Allows Slow Rise Times Carry Out Output for Cascading Divide-by-N Counting Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low-Power TTL Loads or One Low-Power Schottky TTL Load Over the Rated Temperature Range Pin-for-Pin Replacement for CD4017B Triple Diode Protection on All Inputs Pb-Free Packages are Available*
PDIP-16 P SUFFIX CASE 648
16 SOIC-16 D SUFFIX CASE 751B 1 14017BG AWLYWW
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 1) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Value -0.5 to +18.0 -0.5 to VDD + 0.5 10 500 -55 to +125 -65 to +150 260 Unit V V mA mW C C C SOEIAJ-16 F SUFFIX CASE 966
16 MC14017B ALYWG 1 A WL, L YY, Y WW, W G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Indicator
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet.
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2005
1
August, 2005 - Rev. 6
Publication Order Number: MC14017B/D
MC14017B
PIN ASSIGNMENT
Q5 Q1 Q0 Q2 Q6 Q7 Q3 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD RESET CLOCK CE Cout Q9 Q4 Q8
FUNCTIONAL TRUTH TABLE (Positive Logic)
Clock 0 X X Clock Enable X 1 X 0 X Reset 0 0 1 0 0 0 0 Decode Output=n n n Q0 n+1 n n n+1
BLOCK DIAGRAM
CLOCK 14 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Cout VDD = PIN 16 VSS = PIN 8 3 2 4 7 10 1 5 6 9 11 12
CLOCK 13 ENABLE
X 1
X = Don't Care. If n < 5 Carry = "1", Otherwise = "0".
RESET 15
LOGIC DIAGRAM
Q5 1 Q1 2 Q7 6 7 Q3 11 Q9
14 CLOCK CLOCK ENABLE CQ C DQ RR CQ C DQ RR CQ C DQ RR CQ C DQ RR CQ C DQ RR 12 CARRY
13
RESET
15
3 Q0
5 Q6
4 Q2
9 Q3
10 Q4
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MC14017B
II I I II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I I IIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I IIII II IIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIII I I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I III II IIII III I II II IIII I I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIII I II I I I I III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I I I I III II IIII III I II II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIII II IIII I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I I III II IIII I II II IIII I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIII IIIII I I II II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
- 55_C Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 5.0 10 15 5.0 10 15 15 -- Min -- -- -- 25_C 125_C Max Min -- -- -- Typ (Note 2) 0 0 0 Max Min -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 -- -- -- 0.05 0.05 0.05 -- -- -- 0.05 0.05 0.05 -- -- -- "1" Level VOH Vin = 0 or VDD 4.95 9.95 14.95 -- -- -- 4.95 9.95 14.95 -- -- -- 5.0 10 15 4.95 9.95 14.95 -- -- -- Vdc Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) VIL Vdc 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- 2.25 4.50 6.75 2.75 5.50 8.25 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- VIH Vdc 3.5 7.0 11 3.5 7.0 11 3.5 7.0 11 Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) IOH mAdc Source - 3.0 - 0.64 - 1.6 - 4.2 0.64 1.6 4.2 -- -- -- -- -- - 2.4 - 0.51 - 1.3 - 3.4 0.51 1.3 3.4 -- -- -- -- -- - 4.2 - 0.88 - 2.25 - 8.8 0.88 2.25 8.8 - 1.7 - 0.36 - 0.9 - 2.4 0.36 0.9 2.4 -- -- -- -- -- Sink IOL mAdc Input Current Iin 0.1 -- 0.00001 5.0 0.1 7.5 5.0 10 20 1.0 -- mAdc pF Input Capacitance (Vin = 0) Cin Quiescent Current (Per Package) IDD 5.0 10 15 5.0 10 15 5.0 10 20 0.005 0.010 0.015 150 300 600 mAdc Total Supply Current (Notes 3 & 4) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) IT IT = (0.27 mA/kHz) f + IDD IT = (0.55 mA/kHz) f + IDD IT = (0.83 mA/kHz) f + IDD mAdc 2. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in mA (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.0011.
ORDERING INFORMATION
Device MC14017BCP MC14017BCPG MC14017BD MC14017BDR2 MC14017BDR2G MC14017BFEL Package PDIP-16 PDIP-16 (Pb-Free) SOIC-16 SOIC-16 SOIC-16 (Pb-Free) SOEIAJ-16 Shipping 500 Units / Rail 500 Units / Rail 48 Units / Rail 2500 Units / Tape & Reel 2500 Units / Tape & Reel 2000 Units / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I III I III IIIIIIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I III I II I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I IIIII I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII IIIII II I IIIII I IIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I III I I I I I IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I III III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I II I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I I III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I III IIIIIIIIIIIIIIIIIII IIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I II I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII
5. The formulas given are for the typical characteristics only at 25_C. 6. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)
Clock Enable Removal Time
Clock Enable Setup Time
Clock Input Rise and Fall Time
Reset Removal Time
Reset Pulse Width
Clock Frequency
Clock Pulse Width
Turn-Off Delay Time Reset to Cout tPLH = (1.7 ns/pF) CL + 315 ns tPLH = (0.66 ns/pF) CL + 142 ns tPLH = (0.5 ns/pF) CL + 100 ns
Propagation Delay Time Clock to Decode Output tPLH, tPHL = (1.7 ns/pF) CL + 415 ns tPLH, tPHL = (0.66 ns/pF) CL + 197 ns tPLH, tPHL = (0.5 ns/pF) CL + 150 ns
Propagation Delay Time Clock to Cout tPLH, tPHL = (1.7 ns/pF) CL + 315 ns tPLH, tPHL = (0.66 ns/pF) CL + 142 ns tPLH, tPHL = (0.5 ns/pF) CL + 100 ns
Propagation Delay Time Reset to Decode Output tPLH, tPHL = (1.7 ns/pF) CL + 415 ns tPLH, tPHL = (0.66 ns/PF) CL + 197 ns tPLH, tPHL = (0.5 ns/pF) CL + 150 ns
Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
Characteristic
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Symbol
MC14017B
tPLH, tPHL
tPLH, tPHL
tPLH, tPHL
tTLH, tTHL
tTLH, tTHL
tw(H)
tw(H)
tPLH
trem
trem
tsu
fcl
4 VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 Min 420 200 140 350 150 115 750 275 210 500 250 190 250 100 75 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- No Limit Typ (Note 6) 260 100 70 175 75 52 375 135 105 250 125 95 125 50 35 400 175 125 500 230 175 400 175 125 500 230 175 100 50 40 5.0 12 16 1000 460 350 1000 460 350 Max 800 350 250 800 350 250 200 100 80 2.0 5.0 6.7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MHz Unit ns ns ns ns ns ns ns ns ns ns --
MC14017B
VDD Vout Output Sink Drive Decode Outputs ID Carry VGS = VDS = Output Source Drive Clock to desired outputs (S1 to B) S1 to A - VDD Vout - VDD
VSS
VDD VSS
A B
S1 S1
CLOCK Q0 ENABLE Q1 Q2 Q3 Q4 RESET Q5 Q6 Q7 Q8 Q9 CLOCK Cout VSS
(S1 to A)
Clock to 5 thru 9 (S1 to B) VDD Vout
EXTERNAL POWER SUPPLY
Figure 1. Typical Output Source and Output Sink Characteristics Test Circuit
VDD 500 mF ID 0.01 mF CERAMIC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Cout VSS CL CL CL CL CL CL CL CL CL CL CL
CLOCK ENABLE RESET PULSE GENERATOR fc
CLOCK
Figure 2. Typical Power Dissipation Test Circuit
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MC14017B
APPLICATIONS INFORMATION Figure 3 shows a technique for extending the number of decoded output states for the MC14017B. Decoded outputs are sequential within each stage and from stage to stage, with no dead time (except propagation delay).
RESET CLOCK CE MC14017B
Q0 Q1 * * * Q8 Q9
RESET CLOCK CE MC14017B
Q0Q1 * * * Q8 Q9
RESET CLOCK CE MC14017B
Q1 * * * Q8 Q9 8 DECODED OUTPUTS
9 DECODED OUTPUTS CLOCK
8 DECODED OUTPUTS
FIRST STAGE
INTERMEDIATE STAGES
LAST STAGE
Figure 3. Counter Expansion
Pcp CLOCK CLOCK ENABLE trem RESET 20 ns Q0 tPLH Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Cout tPLH tPLH
Ncp trem 20 ns tPHL tPHL tPHL tPHL 50% tPLH tPLH tPLH tTHL 10% tPLH tTHL tPHL tPHL tPHL 90% tTHL tPHL tTLH tTLH tTHL tTHL tsu 20 ns tPLH 20 ns 20 ns
90% 10%
50%
VDD VSS VDD VSS VDD VSS
20 ns tPLH tTLH 90% 10% tTLH tTLH 50% tTHL tTHL
VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL
tPHL tTHL
tTLH
tPLH tTLH tTHL tPLH tTLH tPLH tPHL tTHL tPHL tTHL
tPHL
tTLH
Figure 4. AC Measurement Definition and Functional Waveforms
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MC14017B
PACKAGE DIMENSIONS
PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE T
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL.
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
DIM A B C D F G H J K L M S
INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040
MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
SOIC-16 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
-A-
16 9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
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MC14017B
PACKAGE DIMENSIONS
SOEIAJ-16 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 966-01 ISSUE O
16
9
LE Q1 E HE M_ L DETAIL P
1
8
Z D e A VIEW P
c
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031
b 0.13 (0.005)
M
A1 0.10 (0.004)
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PUBLICATION ORDERING INFORMATION
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MC14017B/D

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